Field of the Invention
The present invention relates to an image sensor.
Description of Related Art
A scanning circuit of a CMOS image sensor is generally designed to perform a synchronous operation. In other words, the scanning circuit of a CMOS image sensor selectively reads information regarding a necessary pixel by synchronously operating a plurality of latches (shift registers). In an image sensor having a pixel matrix of (n+1) rows and (n+1) columns shown in FIG. 8 of Japanese Unexamined Patent Application, First Publication No. 2008-306695, each of a column scanning circuit for selecting a column of pixels and a data output circuit for selecting a row of pixels has latches.
In order for the data output circuit for selecting a row of pixels with high accuracy to exactly capture data, a master clock supplied from a clock supply circuit is supplied to the latches in order from the farthest latch. The data output circuit captures data output from a sense amplification circuit in accordance with a capture clock whose phase is adjusted on the basis of the master clock.
At least (n+1) buffers are required to adjust the phase of the above-described clock. The clock supplied to the buffers changes whenever a pixel for reading a signal changes. Therefore, a buffer corresponding to a pixel on which reading is not performed is also operated at each timing at which the clock changes, and power consumption occurs.